As it is well known, the development of stacking technology for heterogeneous device integration has recently increased in importance.
Stacking of chips, in which two or more integrated circuits or ICs of different types are placed one on the top of the other in a same package, is an alternative to silicon integration and may provide improvements at the system design level in terms of size, cost, speed, power consumption and ease of application for a wide variety of products.
However, successful implementation of the stacking or 3D technology requires dealing with state-of-the-art of assembly processes such as wafer back-grinding, handling, die attach, wirebond and alignment. So, the choice of a stacking or 3D technology depends largely on the application of the final chip so obtained.
In particular, vertical data communication using AC wireless interconnect has been recently presented as very promising stacking or 3D technology for high-bandwidth, high speed applications, as described in the article to Kanda K. et al. entitled “1.27 Gb/s/pin 3 mW/pin wireless superconnect wsc interface scheme”, ISSCC Dig. Tech. Papers, pp. 186-187, February 2003, which is incorporated by reference.
In this field of application, in order to improve the inter-chip communication efficiency, a very accurate and precise alignment of the stacked chips is often required.
Many strategies have been presented to make chip positioning with sub-micron precision possible. Known alignment systems and methods allowing a sub-micron precision are described for instance in the following articles:                Neville K. S Lee, “An-Ultra precision alignment system for Micro-machining”, IEEE ICIT 2002;        M. Olson et al, “Sub-micrometer precision measurement method for wafer level assembly”, International Conference on Solid State Sensors, Actuators and Microsystem June 2003; and        R. J. Drost et al., “Electronic Alignment for Proximity Communication”, ISSCC Dig. Tech. Papers, pp. 144-145, February 2004, all of which are incorporated by reference.        
Also known from U.S. Pat. No. 4,566,193, which issued on Jan. 28, 1986 and which is incorporated by reference, is an electronic vernier which detects and quantifies misalignment between layers of deposited material on a semiconducting wafer, in particular during a semiconductor manufacturing process.
Furthermore, U.S. Pat. No. 6,518,679, which issued on Feb. 11, 2003 and which is incorporated by reference, describes a capacitive alignment structure and method for chip stacking.
Some of these known approaches require expensive and complex servomechanisms, sensors and actuators. Moreover, the methods and systems actually available in the field are typically not standard but are tailored to a specific application of a final stacked device to be realized.